// +build f030x6

// Peripheral: FLASH_Periph  FLASH Registers.
// Instances:
//  FLASH  mmap.FLASH_R_BASE
// Registers:
//  0x00 32  ACR      Access control register.
//  0x04 32  KEYR     Key register.
//  0x08 32  OPTKEYR  OPT key register.
//  0x0C 32  SR       Status register.
//  0x10 32  CR       Control register.
//  0x14 32  AR       Address register.
//  0x18 32  RESERVED Reserved,                                                     0x18.
//  0x1C 32  OBR      Option bytes register.
//  0x20 32  WRPR     Option bytes register.
// Import:
//  stm32/o/f030x6/mmap
package flash

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	LATENCY ACR = 0x01 << 0 //+ LATENCY bit (Latency).
	PRFTBE  ACR = 0x01 << 4 //+ Prefetch Buffer Enable.
	PRFTBS  ACR = 0x01 << 5 //+ Prefetch Buffer Status.
)

const (
	LATENCYn = 0
	PRFTBEn  = 4
	PRFTBSn  = 5
)

const (
	FKEYR KEYR = 0xFFFFFFFF << 0 //+ FPEC Key.
)

const (
	FKEYRn = 0
)

const (
	BSY      SR = 0x01 << 0 //+ Busy.
	PGERR    SR = 0x01 << 2 //+ Programming Error.
	WRPRTERR SR = 0x01 << 4 //+ Write Protection Error.
	EOP      SR = 0x01 << 5 //+ End of operation.
)

const (
	BSYn      = 0
	PGERRn    = 2
	WRPRTERRn = 4
	EOPn      = 5
)

const (
	PG         CR = 0x01 << 0  //+ Programming.
	PER        CR = 0x01 << 1  //+ Page Erase.
	MER        CR = 0x01 << 2  //+ Mass Erase.
	OPTPG      CR = 0x01 << 4  //+ Option Byte Programming.
	OPTER      CR = 0x01 << 5  //+ Option Byte Erase.
	STRT       CR = 0x01 << 6  //+ Start.
	LOCK       CR = 0x01 << 7  //+ Lock.
	OPTWRE     CR = 0x01 << 9  //+ Option Bytes Write Enable.
	ERRIE      CR = 0x01 << 10 //+ Error Interrupt Enable.
	EOPIE      CR = 0x01 << 12 //+ End of operation interrupt enable.
	OBL_LAUNCH CR = 0x01 << 13 //+ Option Bytes Loader Launch.
)

const (
	PGn         = 0
	PERn        = 1
	MERn        = 2
	OPTPGn      = 4
	OPTERn      = 5
	STRTn       = 6
	LOCKn       = 7
	OPTWREn     = 9
	ERRIEn      = 10
	EOPIEn      = 12
	OBL_LAUNCHn = 13
)

const (
	FAR AR = 0xFFFFFFFF << 0 //+ Flash Address.
)

const (
	FARn = 0
)

const (
	OPTERR           OBR = 0x01 << 0  //+ Option Byte Error.
	RDPRT1           OBR = 0x01 << 1  //+ Read protection Level 1.
	RDPRT2           OBR = 0x01 << 2  //+ Read protection Level 2.
	USER             OBR = 0x77 << 8  //+ User Option Bytes.
	IWDG_SW          OBR = 0x01 << 8  //  IWDG SW.
	nRST_STOP        OBR = 0x02 << 8  //  nRST_STOP.
	nRST_STDBY       OBR = 0x04 << 8  //  nRST_STDBY.
	nBOOT1           OBR = 0x10 << 8  //  nBOOT1.
	VDDA_MONITOR     OBR = 0x20 << 8  //  VDDA power supply supervisor.
	RAM_PARITY_CHECK OBR = 0x40 << 8  //  RAM parity check.
	DATA0            OBR = 0xFF << 16 //+ Data0.
	DATA1            OBR = 0xFF << 24 //+ Data1.
)

const (
	OPTERRn = 0
	RDPRT1n = 1
	RDPRT2n = 2
	USERn   = 8
	DATA0n  = 16
	DATA1n  = 24
)
